{
	"version": "1.0",
	"modules": {
		"system": {
			"proto_instances": {
				"/comb_0/M_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/comb_0/S00_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata[15:0]"},
						"TREADY": { "actual": "s_axis_tready[0:0]"},
						"TVALID": { "actual": "s_axis_tvalid[0:0]"}
					}
				},
				"/comb_0/S01_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata[31:16]"},
						"TREADY": { "actual": "s_axis_tready[1:1]"},
						"TVALID": { "actual": "s_axis_tvalid[1:1]"}
					}
				},
				"/dac_0/s_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/hub_0/m00_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m00_axis_tdata"},
						"TREADY": { "actual": "m00_axis_tready"},
						"TVALID": { "actual": "m00_axis_tvalid"}
					}
				},
				"/hub_0/s00_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s00_axis_tdata"},
						"TREADY": { "actual": "s00_axis_tready"},
						"TVALID": { "actual": "s00_axis_tvalid"}
					}
				},
				"/hub_0/s_axi": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARADDR": { "actual": "s_axi_araddr"},
						"ARESETN": { "actual": "aresetn"},
						"ARID": { "actual": "s_axi_arid"},
						"ARLEN": { "actual": "s_axi_arlen"},
						"ARREADY": { "actual": "s_axi_arready"},
						"ARVALID": { "actual": "s_axi_arvalid"},
						"AWADDR": { "actual": "s_axi_awaddr"},
						"AWID": { "actual": "s_axi_awid"},
						"AWREADY": { "actual": "s_axi_awready"},
						"AWVALID": { "actual": "s_axi_awvalid"},
						"BID": { "actual": "s_axi_bid"},
						"BREADY": { "actual": "s_axi_bready"},
						"BVALID": { "actual": "s_axi_bvalid"},
						"RDATA": { "actual": "s_axi_rdata"},
						"RID": { "actual": "s_axi_rid"},
						"RLAST": { "actual": "s_axi_rlast"},
						"RREADY": { "actual": "s_axi_rready"},
						"RVALID": { "actual": "s_axi_rvalid"},
						"WDATA": { "actual": "s_axi_wdata"},
						"WLAST": { "actual": "s_axi_wlast"},
						"WREADY": { "actual": "s_axi_wready"},
						"WSTRB": { "actual": "s_axi_wstrb"},
						"WVALID": { "actual": "s_axi_wvalid"}
					}
				},
				"/ps_0/M_AXI_GP0": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M_AXI_GP0_ACLK"},
						"ARADDR": { "actual": "M_AXI_GP0_ARADDR"},
						"ARBURST": { "actual": "M_AXI_GP0_ARBURST"},
						"ARCACHE": { "actual": "M_AXI_GP0_ARCACHE"},
						"ARID": { "actual": "M_AXI_GP0_ARID"},
						"ARLEN": { "actual": "M_AXI_GP0_ARLEN"},
						"ARLOCK": { "actual": "M_AXI_GP0_ARLOCK"},
						"ARPROT": { "actual": "M_AXI_GP0_ARPROT"},
						"ARQOS": { "actual": "M_AXI_GP0_ARQOS"},
						"ARREADY": { "actual": "M_AXI_GP0_ARREADY"},
						"ARSIZE": { "actual": "M_AXI_GP0_ARSIZE"},
						"ARVALID": { "actual": "M_AXI_GP0_ARVALID"},
						"AWADDR": { "actual": "M_AXI_GP0_AWADDR"},
						"AWBURST": { "actual": "M_AXI_GP0_AWBURST"},
						"AWCACHE": { "actual": "M_AXI_GP0_AWCACHE"},
						"AWID": { "actual": "M_AXI_GP0_AWID"},
						"AWLEN": { "actual": "M_AXI_GP0_AWLEN"},
						"AWLOCK": { "actual": "M_AXI_GP0_AWLOCK"},
						"AWPROT": { "actual": "M_AXI_GP0_AWPROT"},
						"AWQOS": { "actual": "M_AXI_GP0_AWQOS"},
						"AWREADY": { "actual": "M_AXI_GP0_AWREADY"},
						"AWSIZE": { "actual": "M_AXI_GP0_AWSIZE"},
						"AWVALID": { "actual": "M_AXI_GP0_AWVALID"},
						"BID": { "actual": "M_AXI_GP0_BID"},
						"BREADY": { "actual": "M_AXI_GP0_BREADY"},
						"BRESP": { "actual": "M_AXI_GP0_BRESP"},
						"BVALID": { "actual": "M_AXI_GP0_BVALID"},
						"RDATA": { "actual": "M_AXI_GP0_RDATA"},
						"RID": { "actual": "M_AXI_GP0_RID"},
						"RLAST": { "actual": "M_AXI_GP0_RLAST"},
						"RREADY": { "actual": "M_AXI_GP0_RREADY"},
						"RRESP": { "actual": "M_AXI_GP0_RRESP"},
						"RVALID": { "actual": "M_AXI_GP0_RVALID"},
						"WDATA": { "actual": "M_AXI_GP0_WDATA"},
						"WID": { "actual": "M_AXI_GP0_WID"},
						"WLAST": { "actual": "M_AXI_GP0_WLAST"},
						"WREADY": { "actual": "M_AXI_GP0_WREADY"},
						"WSTRB": { "actual": "M_AXI_GP0_WSTRB"},
						"WVALID": { "actual": "M_AXI_GP0_WVALID"}
					}
				},
				"/rx_0/cic_0/M_AXIS_DATA": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_data_tdata"},
						"TREADY": { "actual": "m_axis_data_tready"},
						"TVALID": { "actual": "m_axis_data_tvalid"}
					}
				},
				"/rx_0/cic_0/S_AXIS_CONFIG": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_config_tdata"},
						"TREADY": { "actual": "s_axis_config_tready"},
						"TVALID": { "actual": "s_axis_config_tvalid"}
					}
				},
				"/rx_0/cic_1/M_AXIS_DATA": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_data_tdata"},
						"TREADY": { "actual": "m_axis_data_tready"},
						"TVALID": { "actual": "m_axis_data_tvalid"}
					}
				},
				"/rx_0/cic_1/S_AXIS_CONFIG": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_config_tdata"},
						"TREADY": { "actual": "s_axis_config_tready"},
						"TVALID": { "actual": "s_axis_config_tvalid"}
					}
				},
				"/rx_0/cic_2/M_AXIS_DATA": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_data_tdata"},
						"TREADY": { "actual": "m_axis_data_tready"},
						"TVALID": { "actual": "m_axis_data_tvalid"}
					}
				},
				"/rx_0/cic_2/S_AXIS_CONFIG": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_config_tdata"},
						"TREADY": { "actual": "s_axis_config_tready"},
						"TVALID": { "actual": "s_axis_config_tvalid"}
					}
				},
				"/rx_0/cic_3/M_AXIS_DATA": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_data_tdata"},
						"TREADY": { "actual": "m_axis_data_tready"},
						"TVALID": { "actual": "m_axis_data_tvalid"}
					}
				},
				"/rx_0/cic_3/S_AXIS_CONFIG": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
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						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_config_tdata"},
						"TREADY": { "actual": "s_axis_config_tready"},
						"TVALID": { "actual": "s_axis_config_tvalid"}
					}
				},
				"/rx_0/comb_0/M_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/comb_0/S00_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata[31:0]"},
						"TREADY": { "actual": "s_axis_tready[0:0]"},
						"TVALID": { "actual": "s_axis_tvalid[0:0]"}
					}
				},
				"/rx_0/comb_0/S01_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata[63:32]"},
						"TREADY": { "actual": "s_axis_tready[1:1]"},
						"TVALID": { "actual": "s_axis_tvalid[1:1]"}
					}
				},
				"/rx_0/comb_0/S02_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata[95:64]"},
						"TREADY": { "actual": "s_axis_tready[2:2]"},
						"TVALID": { "actual": "s_axis_tvalid[2:2]"}
					}
				},
				"/rx_0/comb_0/S03_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata[127:96]"},
						"TREADY": { "actual": "s_axis_tready[3:3]"},
						"TVALID": { "actual": "s_axis_tvalid[3:3]"}
					}
				},
				"/rx_0/conv_0/M_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/conv_0/S_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/rx_0/conv_1/M_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/conv_1/S_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/rx_0/dds_0/S_AXIS_PHASE": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_phase_tdata"},
						"TVALID": { "actual": "s_axis_phase_tvalid"}
					}
				},
				"/rx_0/fifo_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/fifo_0/s_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/rx_0/fir_0/M_AXIS_DATA": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_data_tdata"},
						"TVALID": { "actual": "m_axis_data_tvalid"}
					}
				},
				"/rx_0/fir_0/S_AXIS_DATA": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_data_tdata"},
						"TREADY": { "actual": "s_axis_data_tready"},
						"TVALID": { "actual": "s_axis_data_tvalid"}
					}
				},
				"/rx_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/m_axis1": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis1_tdata"},
						"TREADY": { "actual": "m_axis1_tready"},
						"TVALID": { "actual": "m_axis1_tvalid"}
					}
				},
				"/rx_0/output_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/phase_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/rate_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/rate_1/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/rate_2/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/rate_3/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/subset_0/M_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/subset_0/S_AXIS": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/rx_0/vldtr_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/rx_0/vldtr_0/s_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/tx_0/dds_0/S_AXIS_PHASE": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_phase_tdata"},
						"TVALID": { "actual": "s_axis_phase_tvalid"}
					}
				},
				"/tx_0/fifo_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/tx_0/fifo_0/s_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/tx_0/gate_0/s_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARESETN": { "actual": "aresetn"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/tx_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/tx_0/phase_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				},
				"/tx_0/s_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "s_axis_tdata"},
						"TREADY": { "actual": "s_axis_tready"},
						"TVALID": { "actual": "s_axis_tvalid"}
					}
				},
				"/tx_0/zeroer_0/m_axis": {
					"interface": "xilinx.com:interface:axis:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"TDATA": { "actual": "m_axis_tdata"},
						"TREADY": { "actual": "m_axis_tready"},
						"TVALID": { "actual": "m_axis_tvalid"}
					}
				}
			}
		}
	}
}