Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 | Date : Mon Apr 13 14:56:00 2026 | Host : debian running 64-bit Debian GNU/Linux 13 (trixie) | Command : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb | Design : system_wrapper | Device : xc7z020clg400-1 | Speed File : -1 | Design State : Synthesized ----------------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Slice Logic 1.1 Summary of Registers by Type 2. Memory 3. DSP 4. IO and GT Specific 5. Clocking 6. Specific Feature 7. Primitives 8. Black Boxes 9. Instantiated Netlists 1. Slice Logic -------------- +----------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------------+-------+-------+------------+-----------+-------+ | Slice LUTs* | 8573 | 0 | 0 | 53200 | 16.11 | | LUT as Logic | 5801 | 0 | 0 | 53200 | 10.90 | | LUT as Memory | 2772 | 0 | 0 | 17400 | 15.93 | | LUT as Distributed RAM | 128 | 0 | | | | | LUT as Shift Register | 2644 | 0 | | | | | Slice Registers | 12070 | 0 | 0 | 106400 | 11.34 | | Register as Flip Flop | 12070 | 0 | 0 | 106400 | 11.34 | | Register as Latch | 0 | 0 | 0 | 106400 | 0.00 | | F7 Muxes | 0 | 0 | 0 | 26600 | 0.00 | | F8 Muxes | 0 | 0 | 0 | 13300 | 0.00 | +----------------------------+-------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 1.1 Summary of Registers by Type -------------------------------- +-------+--------------+-------------+--------------+ | Total | Clock Enable | Synchronous | Asynchronous | +-------+--------------+-------------+--------------+ | 0 | _ | - | - | | 0 | _ | - | Set | | 0 | _ | - | Reset | | 0 | _ | Set | - | | 0 | _ | Reset | - | | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 136 | Yes | Set | - | | 11934 | Yes | Reset | - | +-------+--------------+-------------+--------------+ 2. Memory --------- +-------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------+------+-------+------------+-----------+-------+ | Block RAM Tile | 6 | 0 | 0 | 140 | 4.29 | | RAMB36/FIFO* | 4 | 0 | 0 | 140 | 2.86 | | RAMB36E1 only | 4 | | | | | | RAMB18 | 4 | 0 | 0 | 280 | 1.43 | | RAMB18E1 only | 4 | | | | | +-------------------+------+-------+------------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 3. DSP ------ +----------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------+------+-------+------------+-----------+-------+ | DSPs | 92 | 0 | 0 | 220 | 41.82 | | DSP48E1 only | 92 | | | | | +----------------+------+-------+------------+-----------+-------+ 4. IO and GT Specific --------------------- +-----------------------------+------+-------+------------+-----------+--------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-----------------------------+------+-------+------------+-----------+--------+ | Bonded IOB | 61 | 0 | 0 | 125 | 48.80 | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | Bonded IOPADs | 130 | 0 | 0 | 130 | 100.00 | | PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 | | PHASER_REF | 0 | 0 | 0 | 4 | 0.00 | | OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 | | IN_FIFO | 0 | 0 | 0 | 16 | 0.00 | | IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 | | IBUFDS | 1 | 0 | 0 | 121 | 0.83 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 | | ILOGIC | 0 | 0 | 0 | 125 | 0.00 | | OLOGIC | 18 | 0 | 0 | 125 | 14.40 | | ODDR | 18 | | | | | +-----------------------------+------+-------+------------+-----------+--------+ 5. Clocking ----------- +------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +------------+------+-------+------------+-----------+-------+ | BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | | BUFIO | 0 | 0 | 0 | 16 | 0.00 | | MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 | | PLLE2_ADV | 1 | 0 | 0 | 4 | 25.00 | | BUFMRCE | 0 | 0 | 0 | 8 | 0.00 | | BUFHCE | 0 | 0 | 0 | 72 | 0.00 | | BUFR | 0 | 0 | 0 | 16 | 0.00 | +------------+------+-------+------------+-----------+-------+ 6. Specific Feature ------------------- +-------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------+------+-------+------------+-----------+-------+ | BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | | CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | | DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | | EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | | FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | | ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | | STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | | XADC | 0 | 0 | 0 | 1 | 0.00 | +-------------+------+-------+------------+-----------+-------+ 7. Primitives ------------- +-----------+-------+----------------------+ | Ref Name | Used | Functional Category | +-----------+-------+----------------------+ | FDRE | 11934 | Flop & Latch | | SRL16E | 2640 | Distributed Memory | | LUT2 | 1576 | LUT | | LUT4 | 1467 | LUT | | LUT6 | 1116 | LUT | | LUT3 | 746 | LUT | | CARRY4 | 703 | CarryLogic | | LUT1 | 639 | LUT | | LUT5 | 418 | LUT | | FDSE | 136 | Flop & Latch | | BIBUF | 130 | IO | | RAMD32 | 128 | Distributed Memory | | DSP48E1 | 92 | Block Arithmetic | | IBUF | 32 | IO | | OBUFT | 22 | IO | | OBUF | 21 | IO | | ODDR | 18 | IO | | BUFG | 5 | Clock | | SRLC32E | 4 | Distributed Memory | | RAMB36E1 | 4 | Block Memory | | RAMB18E1 | 4 | Block Memory | | PS7 | 1 | Specialized Resource | | PLLE2_ADV | 1 | Clock | | IBUFDS | 1 | IO | +-----------+-------+----------------------+ 8. Black Boxes -------------- +----------+------+ | Ref Name | Used | +----------+------+ 9. Instantiated Netlists ------------------------ +----------+------+ | Ref Name | Used | +----------+------+