pavel-demin user port_selector 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog port_selector xilinx_anylanguagesynthesis_view_fileset viewChecksum a0d31203 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog port_selector xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum a0d31203 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 90c8036b cfg in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din in 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DOUT_WIDTH Dout Width 32 xilinx_anylanguagesynthesis_view_fileset ../../../cores/port_selector.v verilogSource CHECKSUM_a0d31203 xilinx_anylanguagebehavioralsimulation_view_fileset ../../../cores/port_selector.v verilogSource xilinx_xpgui_view_fileset xgui/port_selector_v1_0.tcl tclSource CHECKSUM_90c8036b XGUI_VERSION_2 port_selector_v1_0 DOUT_WIDTH Dout Width 32 Component_Name port_selector_v1_0 zynq /BaseIP port_selector_v1_0 package_project Pavel Demin https://github.com/pavel-demin/red-pitaya-notes 1 2025-11-21T13:41:42Z 2021.2