pavel-demin user axi_hub 1.0 b00_bram EN b00_bram_en DOUT b00_bram_rdata DIN b00_bram_wdata WE b00_bram_we ADDR b00_bram_addr CLK b00_bram_clk RST b00_bram_rst b01_bram EN b01_bram_en DOUT b01_bram_rdata DIN b01_bram_wdata WE b01_bram_we ADDR b01_bram_addr CLK b01_bram_clk RST b01_bram_rst b02_bram EN b02_bram_en DOUT b02_bram_rdata DIN b02_bram_wdata WE b02_bram_we ADDR b02_bram_addr CLK b02_bram_clk RST b02_bram_rst b03_bram EN b03_bram_en DOUT b03_bram_rdata DIN b03_bram_wdata WE b03_bram_we ADDR b03_bram_addr CLK b03_bram_clk RST b03_bram_rst b04_bram EN b04_bram_en DOUT b04_bram_rdata DIN b04_bram_wdata WE b04_bram_we ADDR b04_bram_addr CLK b04_bram_clk RST b04_bram_rst b05_bram EN b05_bram_en DOUT b05_bram_rdata DIN b05_bram_wdata WE b05_bram_we ADDR b05_bram_addr CLK b05_bram_clk RST b05_bram_rst m00_axis TDATA m00_axis_tdata TVALID m00_axis_tvalid TREADY m00_axis_tready m01_axis TDATA m01_axis_tdata TVALID m01_axis_tvalid TREADY m01_axis_tready m02_axis TDATA m02_axis_tdata TVALID m02_axis_tvalid TREADY m02_axis_tready m03_axis TDATA m03_axis_tdata TVALID m03_axis_tvalid TREADY m03_axis_tready m04_axis TDATA m04_axis_tdata TVALID m04_axis_tvalid TREADY m04_axis_tready m05_axis TDATA m05_axis_tdata TVALID m05_axis_tvalid TREADY m05_axis_tready s00_axis TDATA s00_axis_tdata TVALID s00_axis_tvalid TREADY s00_axis_tready s01_axis TDATA s01_axis_tdata TVALID s01_axis_tvalid TREADY s01_axis_tready s02_axis TDATA s02_axis_tdata TVALID s02_axis_tvalid TREADY s02_axis_tready s03_axis TDATA s03_axis_tdata TVALID s03_axis_tvalid TREADY s03_axis_tready s04_axis TDATA s04_axis_tdata TVALID s04_axis_tvalid TREADY s04_axis_tready s05_axis TDATA s05_axis_tdata TVALID s05_axis_tvalid TREADY s05_axis_tready s_axi AWID s_axi_awid AWADDR s_axi_awaddr AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WLAST s_axi_wlast WVALID s_axi_wvalid WREADY s_axi_wready BID s_axi_bid BVALID s_axi_bvalid BREADY s_axi_bready ARID s_axi_arid ARADDR s_axi_araddr ARLEN s_axi_arlen ARVALID s_axi_arvalid ARREADY s_axi_arready RID s_axi_rid RDATA s_axi_rdata RLAST s_axi_rlast RVALID s_axi_rvalid RREADY s_axi_rready aresetn RST aresetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF m00_axis:m01_axis:m02_axis:m03_axis:m04_axis:m05_axis:s00_axis:s01_axis:s02_axis:s03_axis:s04_axis:s05_axis:s_axi ASSOCIATED_RESET aresetn s_axi reg0 0 4294967296 32 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_hub xilinx_anylanguagesynthesis_view_fileset viewChecksum 5b27e1e5 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_hub xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 5b27e1e5 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum e58f80a4 aclk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awid in 11 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wstrb in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wlast in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bid out 11 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arid in 11 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arlen in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rid out 11 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 cfg_data out 1023 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sts_data in 1023 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b00_bram_clk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b00_bram_rst out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b00_bram_en out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b00_bram_we out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b00_bram_addr out 21 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b00_bram_wdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b00_bram_rdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 8 s00_axis_tdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axis_tdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 b01_bram_clk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b01_bram_rst out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b01_bram_en out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b01_bram_we out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b01_bram_addr out 21 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b01_bram_wdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b01_bram_rdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 8 s01_axis_tdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s01_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s01_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m01_axis_tdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m01_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m01_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 b02_bram_clk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b02_bram_rst out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b02_bram_en out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b02_bram_we out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b02_bram_addr out 21 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b02_bram_wdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b02_bram_rdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 8 s02_axis_tdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s02_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s02_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m02_axis_tdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m02_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m02_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 b03_bram_clk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b03_bram_rst out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b03_bram_en out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b03_bram_we out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b03_bram_addr out 21 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b03_bram_wdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b03_bram_rdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 8 s03_axis_tdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s03_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s03_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m03_axis_tdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m03_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m03_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 b04_bram_clk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b04_bram_rst out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b04_bram_en out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b04_bram_we out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b04_bram_addr out 21 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b04_bram_wdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b04_bram_rdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 8 s04_axis_tdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s04_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s04_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m04_axis_tdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m04_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m04_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 b05_bram_clk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b05_bram_rst out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b05_bram_en out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b05_bram_we out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b05_bram_addr out 21 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b05_bram_wdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation b05_bram_rdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 8 s05_axis_tdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s05_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s05_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m05_axis_tdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m05_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m05_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 CFG_DATA_WIDTH Cfg Data Width 1024 STS_DATA_WIDTH Sts Data Width 1024 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../../../modules/inout_buffer.v verilogSource ../../../modules/input_buffer.v verilogSource ../../../modules/output_buffer.v verilogSource ../../../cores/axi_hub.v verilogSource CHECKSUM_789c658a xilinx_anylanguagebehavioralsimulation_view_fileset ../../../modules/inout_buffer.v verilogSource ../../../modules/input_buffer.v verilogSource ../../../modules/output_buffer.v verilogSource ../../../cores/axi_hub.v verilogSource xilinx_xpgui_view_fileset xgui/axi_hub_v1_0.tcl tclSource CHECKSUM_e58f80a4 XGUI_VERSION_2 axi_hub_v1_0 CFG_DATA_WIDTH Cfg Data Width 1024 STS_DATA_WIDTH Sts Data Width 1024 Component_Name axi_hub_v1_0 zynq /BaseIP axi_hub_v1_0 package_project Pavel Demin https://github.com/pavel-demin/red-pitaya-notes 1 2025-11-21T13:31:12Z 2021.2