pavel-demin user fsk_rx_core 1.0 rstn RST rstn POLARITY ACTIVE_LOW clk CLK clk ASSOCIATED_RESET rstn xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog fsk_rx_core xilinx_anylanguagesynthesis_view_fileset viewChecksum c27e5ce6 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog fsk_rx_core xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum c27e5ce6 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 35ebc586 clk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rstn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_i in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation valid_i in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_window in 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_limiter_en in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_half_bit in 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bit_raw_o out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bit_sync_o out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation valid_o out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bit_sync_valid_o out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation acc_o out 31 0 reg signed xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 32 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../../../cores/fsk_rx_core.v verilogSource CHECKSUM_c27e5ce6 xilinx_anylanguagebehavioralsimulation_view_fileset ../../../cores/fsk_rx_core.v verilogSource xilinx_xpgui_view_fileset xgui/fsk_rx_core_v1_0.tcl tclSource CHECKSUM_35ebc586 XGUI_VERSION_2 fsk_rx_core_v1_0 DATA_WIDTH Data Width 32 Component_Name fsk_rx_core_v1_0 zynq /BaseIP fsk_rx_core_v1_0 package_project Pavel Demin https://github.com/pavel-demin/red-pitaya-notes 1 2026-04-16T10:48:49Z 2021.2