pavel-demin user edge_detector 1.0 aclk CLK aclk xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog edge_detector xilinx_anylanguagesynthesis_view_fileset viewChecksum ec0237d6 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog edge_detector xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum ec0237d6 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 aclk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset ../../../cores/edge_detector.v verilogSource CHECKSUM_ec0237d6 xilinx_anylanguagebehavioralsimulation_view_fileset ../../../cores/edge_detector.v verilogSource xilinx_xpgui_view_fileset xgui/edge_detector_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 edge_detector_v1_0 Component_Name edge_detector_v1_0 zynq /BaseIP edge_detector_v1_0 package_project Pavel Demin https://github.com/pavel-demin/red-pitaya-notes 1 2026-04-16T10:48:03Z 2021.2