pavel-demin user axis_ram_writer 1.0 s_axis TDATA s_axis_tdata TVALID s_axis_tvalid TREADY s_axis_tready m_axi AWID m_axi_awid AWADDR m_axi_awaddr AWLEN m_axi_awlen AWSIZE m_axi_awsize AWBURST m_axi_awburst AWCACHE m_axi_awcache AWVALID m_axi_awvalid AWREADY m_axi_awready WID m_axi_wid WDATA m_axi_wdata WSTRB m_axi_wstrb WLAST m_axi_wlast WVALID m_axi_wvalid WREADY m_axi_wready BVALID m_axi_bvalid BREADY m_axi_bready aresetn RST aresetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF s_axis:m_axi ASSOCIATED_RESET aresetn m_axi 4294967296 64 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axis_ram_writer xilinx_anylanguagesynthesis_view_fileset viewChecksum a3d92f04 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axis_ram_writer xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum a3d92f04 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 2656a2da aclk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation min_addr in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_data in 15 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sts_data out 15 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awid out 5 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awlen out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awcache out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awaddr out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_wid out 5 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wstrb out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wdata out 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_bvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_bready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 63 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ADDR_WIDTH Addr Width 16 AXI_ID_WIDTH Axi Id Width 6 AXI_ADDR_WIDTH Axi Addr Width 32 AXI_DATA_WIDTH Axi Data Width 64 AXIS_TDATA_WIDTH Axis Tdata Width 64 FIFO_WRITE_DEPTH Fifo Write Depth 512 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../../../modules/output_buffer.v verilogSource ../../../cores/axis_ram_writer.v verilogSource CHECKSUM_491a4766 xilinx_anylanguagebehavioralsimulation_view_fileset ../../../modules/output_buffer.v verilogSource ../../../cores/axis_ram_writer.v verilogSource xilinx_xpgui_view_fileset xgui/axis_ram_writer_v1_0.tcl tclSource CHECKSUM_2656a2da XGUI_VERSION_2 axis_ram_writer_v1_0 ADDR_WIDTH Addr Width 16 AXI_ID_WIDTH Axi Id Width 6 AXI_ADDR_WIDTH Axi Addr Width 32 AXI_DATA_WIDTH Axi Data Width 64 AXIS_TDATA_WIDTH Axis Tdata Width 64 FIFO_WRITE_DEPTH Fifo Write Depth 512 Component_Name axis_ram_writer_v1_0 zynq /BaseIP axis_ram_writer_v1_0 package_project XPM_FIFO Pavel Demin https://github.com/pavel-demin/red-pitaya-notes 1 2026-04-16T10:44:30Z 2021.2