pavel-demin user axis_packetizer 1.0 m_axis TDATA m_axis_tdata TLAST m_axis_tlast TVALID m_axis_tvalid TREADY m_axis_tready s_axis TDATA s_axis_tdata TVALID s_axis_tvalid TREADY s_axis_tready aresetn RST aresetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF m_axis:s_axis ASSOCIATED_RESET aresetn xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axis_packetizer xilinx_anylanguagesynthesis_view_fileset viewChecksum 0a8b7413 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axis_packetizer xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 0a8b7413 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c32bfc87 aclk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_data in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 m_axis_tdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation AXIS_TDATA_WIDTH Axis Tdata Width 32 CNTR_WIDTH Cntr Width 32 CONTINUOUS Continuous FALSE ALWAYS_READY Always Ready FALSE choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../../../cores/axis_packetizer.v verilogSource CHECKSUM_0a8b7413 xilinx_anylanguagebehavioralsimulation_view_fileset ../../../cores/axis_packetizer.v verilogSource xilinx_xpgui_view_fileset xgui/axis_packetizer_v1_0.tcl tclSource CHECKSUM_c32bfc87 XGUI_VERSION_2 axis_packetizer_v1_0 AXIS_TDATA_WIDTH Axis Tdata Width 32 CNTR_WIDTH Cntr Width 32 CONTINUOUS Continuous FALSE ALWAYS_READY Always Ready FALSE Component_Name axis_packetizer_v1_0 zynq /BaseIP axis_packetizer_v1_0 package_project Pavel Demin https://github.com/pavel-demin/red-pitaya-notes 1 2026-04-16T10:42:42Z 2021.2